In a system such as a watch IC where small current-consumption characteristics, that is, low power characteristics, are required, a constant voltage generating circuit (regulator) is conventionally used as the power supply for an internal circuit. The constant voltage generating circuit lowers an externally-supplied power supply voltage and generates a regulated voltage. An internal circuit, such as a watch IC, is driven by this regulated voltage. Such a constant voltage generating circuit is also used as an analog-basis bias power supply.
FIG. 8 is a circuit diagram showing the configuration of a typical constant voltage generating circuit. As shown in FIG. 8, the constant voltage generating circuit generates the reference voltage by a reference voltage generation source 1 based on the power supply voltage, amplifies the current by a differential amplifier 2, and performs fine adjustment and feedback control by an output stage 3 to generate a desired output voltage. The power supply voltage is given by the potential difference between a positive power supply potential VDD and a negative power supply potential VSS. The potential of the positive power supply potential VDD is given to a positive power supply line 5, and the potential of the negative power supply potential VSS is given to a negative power supply line 4. In general, the negative power supply is used for a watch IC with the positive power supply potential VDD as the ground potential.
The reference voltage generation source 1 can comprise, for example, two P-channel MOS transistors (hereinafter called PMOS transistors) 11 and 12 and two N-channel MOS transistors (hereinafter called NMOS transistors) 13 and 14, each of which configure a current mirror circuit, and a resistor 15.
The source of the first PMOS transistor 11 is connected to one end of the resistor 15. The other end of the resistor 15 is connected to the positive power supply line 5. The gate of the first PMOS transistor 11 is connected to the gate and the drain of the second PMOS transistor 12 and to the drain of the second NMOS transistor 14.
The drain of the first PMOS transistor 11 is connected to the drain and the gate of the first NMOS transistor 13 and to the gate of the second NMOS transistor 14. The source of the second PMOS transistor 12 is connected to the positive power supply line 5. The source of the first NMOS transistor 13 and the source of the second NMOS transistor 14 are connected to the negative power supply line 4. A connection node 16 between the drain of the second PMOS transistor 12 and the drain of the second NMOS transistor 14 is the output terminal of the reference voltage generation source 1 from which a first potential REF1 is output as the reference voltage.
A node 16, which is the output terminal of the reference voltage generation source 1, is connected to one of the input terminals of the differential amplifier 2 and to an output stage 3. The other input terminal and the output terminal of the differential amplifier 2 are connected to the output stage 3. The output stage 3 comprises a phase compensating capacitor 31, a third NMOS transistor 32 for output driving, a fourth NMOS transistor 33 that adds a predetermined potential difference (in this case, the positive threshold Vth of the NMOS transistor) to the potential of a regulated voltage output terminal 30 (regulated voltage VREG), and a third PMOS transistor 34 that is the constant current source.
The output terminal of the differential amplifier 2 is connected, via the phase compensating capacitor 31, to the regulated voltage output terminal 30, to the drain of the third NMOS transistor 32, and to the source and the bulk of the fourth NMOS transistor 33. The output terminal of the differential amplifier 2 is connected also to the gate of the third NMOS transistor 32. The source of the third NMOS transistor 32 is connected to the negative power supply line 4. The drain and the gate of the fourth NMOS transistor 33 are connected to the other input terminal of the differential amplifier 2 and to the drain of the third PMOS transistor 34. That is, a second potential REF2, which is output from the drain of the fourth NMOS transistor 33, is applied to the other input terminal of the differential amplifier 2.
The gate of the third PMOS transistor 34 is connected to the node 16 that is the output terminal of the reference voltage generation source 1. That is, the first potential REF1 is applied to the gate of the third PMOS transistor 34. The source of the third PMOS transistor 34 is connected to the positive power supply line 5.
The configuration described above causes the differential amplifier 2 to operate so that the potential of the regulated voltage output terminal 30 is set to the potential generated by adding the positive threshold Vth of the fourth NMOS transistor 33 to the first potential REF1. This operation is the regulator operation.
FIG. 9 shows the potential changes in the parts when the constant voltage generating circuit shown in FIG. 8 described above is started. When the power is turned on and the potential of the negative power supply line 4 becomes the negative power supply potential VSS as shown in FIG. 9(a), the first potential REF1 changes gradually from the positive power supply potential VDD to the negative power supply potential VSS side and, after the period T1 is elapsed from the power-on time, becomes stable at a constant potential as shown in FIG. 9(b). The second potential REF2 once drops to the negative power supply potential VSS side and, after that, becomes stable at the same potential as that of the first potential REF1 as shown in FIG. 9(c). When the first potential REF1 and the second potential REF2 become stable at the same potential, the regulated voltage VREG becomes a stable potential as shown in FIG. 9(d).
A constant voltage generating circuit, especially, a constant voltage generating circuit for generating a driving voltage for driving a watch IC, is required that the current consumption is low as described above, that the startability from the time the power is turned on to the time the potential becomes stable is good, and that the output potential is stable against power supply voltage variations.
The following describes the startability required for the constant voltage generating circuit described above. The detailed transitional operation performed until the potential of the regulated voltage VREG becomes stable is as follows. Immediately after the power is turned on, the gate-bulk capacitor C between the phase compensating capacitor 31 and the third NMOS transistor 32 is not charged. Therefore, the potential of the regulated voltage VREG is almost equal to the negative power supply potential VSS (FIG. 9(d)). In addition, immediately after the power is turned on, the gate bias (first potential REF1) of the third PMOS transistor 34 is low. Therefore, the current supply capacity of the third PMOS transistor 34 is too low to quickly charge the gate-bulk capacitor C between the phase compensating capacitor 31 and the third NMOS transistor 32.
Therefore, there is a period T1 required until the regulated voltage VREG becomes almost equal to the power supply voltage. When the output potential (first potential REF1) of the reference voltage generation source 1 becomes stable and the third PMOS transistor 34 can supply a predetermined current, the gate-bulk capacitor C between the phase compensating capacitor 31 and the third NMOS transistor 32 is charged. This makes the potential of the regulated voltage VREG equal to a desired potential.
As described above, the startability of the constant voltage generating circuit having the configuration shown in FIG. 8 depends on the startability of the reference voltage generation source 1. Especially, for a watch IC that requires small current-consumption characteristics, the operating current is small and the time (period T1) to the convergence of the stable operating point gets longer because the reference voltage generation source 1 comprises the high-resistance resistor 15 and high-impedance (long channel length L) MOS transistors 11, 12, 13, and 14.
This period T1, which varies according to the threshold Vth of the MOS transistors 11, 12, 13, and 14, the ambient temperature, and the applied negative power supply potential VSS, takes about a few milliseconds at room temperature and, takes a few seconds to tens of seconds at low temperature. Therefore, when the constant voltage generating circuit shown in FIG. 8 is used as the power supply of an internal circuit, the problem is that the current consumption at start time increases because the regulated voltage VREG is almost equal to the power supply voltage. When this constant voltage generating circuit is used as an analog-based bias power supply, the problem is that a malfunction may occur because an appropriate bias voltage cannot be supplied at least for the period T1.
Those startability problems can be solved by temporarily increasing the current that flows in the reference voltage generation source 1 immediately after the power is turned on to accelerate the convergence to the stable operating point. The applicant already proposed an invention for improving the startability of the reference voltage generation source 1 (for example, see Patent Document 1). In this invention, a capacitor 17 is connected between the output node 16, which is the output terminal of the reference voltage generation source 1, and the negative power supply line 4 as shown in FIG. 10. The capacitor 17 is not charged when the power is turned on. Therefore, the output node 16 is forced to be lowered to the negative power supply potential VSS. This causes a large current to flow temporarily in the reference voltage generation source 1 to converge the potential quickly to the stable operating point.
However, a later study indicates that the invention described above has a problem with the output potential stability against power supply voltage variations, which is another requirement for the constant voltage generating circuit described above, and, as a result, does not give full stability in some cases.
For example, when a system is driven using a power supply stored in the secondary battery by a power generation device, for example, when a solar watch is driven by a solar battery system, the power supply voltage varies according to the power generation amount. If the invention is applied to such a system to accelerate the convergence to the stable operating point using a capacitor as described above, the capacitor added to improve the startability causes the output potential to vary according to the power supply variation.
For example, when the negative power supply potential VSS varies as shown in FIG. 11, the potential variation of the power supply is superimposed directly on the output potential because the charged voltage of the capacitor 17 is retained and, as a result, the potential of the output node 16 of the reference voltage generation source 1 varies according to the power supply variation. Therefore, the output potential stability against the power supply variation is low. On the other hand, the capacity of the capacitor 17, if decreased, can weaken the effect of the power supply variation, in which case, however, the system does not achieve the full effect of startability improvement.
On the other hand, Japanese Patent Laid-Open Publication No. Sho 62-296213 proposes a method for improving the output potential stability against power supply voltage variations. The constant voltage circuit disclosed in this document comprises a current mirror circuit and a first constant voltage device wherein the non-reference potential side terminal of the first constant voltage device is an output terminal, and the constant voltage circuit further comprises a series circuit, composed of a starting resistor and a second constant voltage device, and a switching device connected between the terminals on the non-reference potential side of the first and second constant voltage devices.
In this configuration, the switching device is conducted immediately after the start to flow the starting current and start the constant voltage circuit and, after the conduction, the switching device is turned off. In the first on state, this switching device supplies the starting current to the first constant voltage device as a bias to initially start the constant voltage circuit and, in the second off state, stops the supply of the starting current to prevent the effect of the power supply voltage variations.
In addition to the configuration described above, a constant voltage circuit is also proposed in which the gate potential of a transistor, which constitutes the current mirror circuit in the constant voltage generating circuit, is controlled to increase the operating current so that the output potential not dependent on the power supply voltage variations is provided and, at the same time, a stable potential is obtained shortly after the power is turned on (for example, see Patent Documents 2-5).
Patent Document 1: Registered utility model 2594470
Patent Document 2: Japanese Patent Laid-Open Publication No. 2002-132359
Patent Document 3: Japanese Patent No. 3149992
Patent Document 4: Japanese Patent Laid-Open Publication No. Hei 09-265329
Patent Document 5: Japanese Patent Laid-Open Publication No. Hei 05-204480
This constant voltage generating circuit comprises, for example, a reference voltage generation source that generates a reference voltage for generating a regulated voltage based on the power supply voltage and gate control means that controls the gate potential of a transistor constituting the current mirror circuit so that the amount of current, which flows in the current mirror circuit included in the reference voltage generation source, increases for a fixed period immediately after the power is turned on.
The gate control means controls the gate potential of the transistor. Turning on the gate increases the operating current of the current mirror circuit and produces a stable potential shortly after the power supply is turned on. Turning off the gate prevents output potential variations caused by power supply voltage variations.
FIG. 12 is a circuit diagram showing the configuration of a constant voltage generating circuit that controls the gate potential of the current mirror circuit. The circuit shown in FIG. 12 is an example based on the configuration shown in FIG. 8 described above. This circuit configuration comprises the constant voltage generating circuit shown in FIG. 8 and further comprises switching means 71 and switching control means 72 that performs the on/off control of the switching means 71.
The switching means 71 is connected between the output node 16 and the negative power supply line 4, wherein the gates of the first and second PMOS transistors 11 and 12, which configure the current mirror circuit of the reference voltage generation source 1, are connected to the output node 16 that is the output terminal of the reference voltage generation source 1.
The switching control means 72 outputs the control signal that instantaneously closes (on) the switching means 71 immediately after the power is turned on. This causes the switching means 71 to be closed for a fixed period of time immediately after the power is turned on and, after that, to be opened (off). The switching means 71 is configured, for example, by a MOS transistor.
For a fixed period of time immediately after the power is turned on, the gate potential of the first PMOS transistor 11 and the gate potential of the second PMOS transistor 12 are controlled by the switching means 71 and the switching control means 72. Therefore, the switching means 71 and the switching control means 72 have the function equivalent to the gate control means. In addition, because the switching means 71 and the switching control means 72 connect the output node 16, which is the output terminal of the reference voltage generation source 1, to the negative power supply line 4, they have the function equivalent to the base voltage control means for a fixed period of time after the power is turned on.
FIG. 13 is a circuit diagram of the switching control means 72 that comprises a resistor 73, a capacitor 74, and an inverter 75. The resistor 73 and the capacitor 74 are connected in series between the positive power supply potential VDD and the negative power supply potential VSS. The input terminal of the inverter 75 is connected to a connection node 76 between the resistor 73 and the capacitor 74. The control signal, which controls the opening/closing of the switching means 71, is output from an output terminal 77 of the inverter 75.
FIG. 14 is a waveform diagram showing the potential change when the switching control means 72 shown in FIG. 13 is started. As shown in FIG. 14(b), the potential of the connection node 76 becomes the negative power supply potential VSS at the same time the power is turned on and the potential of the negative power supply line 4 becomes the negative power supply potential VSS (FIG. 14(a)). After that, the potential of the connection node 76 is gradually changed to the positive power supply potential VDD side as the capacitor 74 is charged.
As shown in FIG. 14(c), the potential of the output terminal 77 of the inverter 75 remains at the positive power supply potential VDD after the power is turned on and before the potential of the connection node 76 reaches ½ of the power supply voltage (VSS/2), and becomes the negative power supply potential VSS when the potential of the connection node 76 becomes higher than ½ of the power supply voltage (VSS/2) and enters the positive power supply potential VDD side. The switching means 71 is in the closed state during the period T2 from the time the power is turned on to the time the potential of the output terminal 77 of the inverter 75 is inverted from the positive power supply potential VDD to the negative power supply potential VSS.
However, the problem with the constant voltage circuit described above is that the switching control means 72 must be provided separately, because the circuit has a configuration in which the on/off state of the switching means 71 is controlled by means of the switching control means 72. The period of the closed state generated by this switching control means 72 immediately after the power is turned on is determined based on the charging time of the capacitor 74. Therefore, to reduce this period T2, the time constant can be reduced by decreasing the resistance of the resistor 73 or decreasing the capacitance of the capacitor 74. However, in this configuration where a large current flows in the switching control means 72 in a short period of time, there is a problem that the current resistance characteristics of the devices configuring the switching control means 72, as well as the noises generated in the switch current, must be taken into consideration.